DesignWare IP

UCIe (D2D) PHY (5nm) and Controller

16Gbps @TSMCN5 Q3, 2022 IP Ready, Q3, 2024 MP

UCIe (D2D) PHY (3nm) and Controller

20Gbps @TSMC N3E/P Q4, 2023 T/O

 High Yield Rate Small Area size Low   power

 Flexible Combination Time to Market  Cost Saving

 IO Die & Computing Die：

 ◆ IO 3-5V vs 3nm, 1.1V

 ◆ Density：3nm vs 5nm 1.6x

UCIe Advanced Package 

The D2DIP MCM

5/4nm(8 channels,48Tx/48Rx per channel) 

◆12.3Tbps data rate @16G per bit per PHY 

◆9.2Tbps data rate @12G per bit per PHY 

3nm(8 channels, 64 Tx/64Rx per channel) 

◆16.38Tbps data rate @16G per bit per PHY

UCIe Standard Package

The D2DIP MCM

◆320Gbps @10G per bit per PHY @5nm

◆246Gbps @8G per bit per PHY @7/6nm 

◆205Gbps @6.4G per bit per PHY @12nm

LPDDR4x/5 IP